Electronic devices often employ multiple semiconductor components such as semiconductor die or packaged components. Some packaged components use a leadframe for support during the packaging process. In some packaging processes, the leadframe is removed after other parts of the package are formed. An example of such a package is a bump chip carrier (BCC) package. Unfortunately, use of a leadframe tends to increase package size and thickness.
One method of reducing the size of chip packages is to stack components vertically so as to increase the effective circuit density. However, stacking components vertically tends to be practical only if at least some of the stacked components can be electrically coupled to each other. If such coupling is unavailable or limited, the size advantage offered by vertical stacking tends to be unrealized. For these and other reasons, improved semiconductor packages and packaging methods are needed to realize compact circuit packages of increasing circuit density.